This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-294981, filed on Sep. 27, 2000, the entire contents of which are incorporated by reference.
1. Field of the Invention
The present invention relates to a method of forming a pattern, and in particular, to an improvement on the method of forming a multi-layer resist pattern, which is designed to be employed in the step of lithography in the manufacturing process of semiconductor device.
2. Description of the Related Art
According to the conventional method, a multi-layer resist pattern has been formed as follows. First of all, as shown in FIGS. 1A to 1C, a lower resist film 53, an SOG film 54 and an upper resist film 55 are successively deposited on the surface of a working substrate (a substrate to be worked) such as a silicon substrate 51 bearing on the surface thereof with a silicon oxide film 52. Then, as shown FIGS. 1D to 1F, the upper resist film 55 is patterned to form an upper resist pattern 55a, which is then employed as a mask for successively etching the SOG film 54 and the lower resist film 53, thereby obtaining a multi-layer resist pattern.
However, this conventional method of forming a multi-layer resist pattern is accompanied with a problem that on the occasion of patterning the upper resist film 55, the dimension of the resultant upper resist pattern is caused to fluctuate depending on the changes in thickness of the SOG film 54.
By the way, in the ordinary lithography process, an inspection for checking the dimension of pattern and also an inspection for checking the relative position between the present pattern and the pattern formed in a previous step are performed. When the resist pattern thus formed is found as being off-specification in these inspections, the lithography process is required to be redone.
If the lithography process is redone due to the off-specification of the pattern in the conventional method of forming a multi-layer resist pattern, it is required at first to remove the upper resist pattern 55a/the SOG film 54a/the lower resist film 53a in stepwise and by a suitable treatment adjusted for each film. This re-work of lithography process however is very troublesome.
Meanwhile, there is also known another conventional method for forming a multi-layer resist pattern, which is featured in the employment of a two-layer structure instead of the aforementioned three-layer structure, wherein Si is incorporated into the upper resist layer to thereby enhancing the etching resistance thereof relative to the lower resist layer.
According to this method, since the upper resist pattern can be directly formed on the surface of the lower resist layer, the SOG film is no longer required to be formed. Therefore, the problem of the fluctuation of dimension which is accompanied with the aforementioned three-layer structure can be overcome by the employment of this two-layer structure. However, the aforementioned problem of troublesome re-work of lithography process will be still left remained when the pattern is found defective.
Additionally, when the content of Si is increased for providing the upper resist layer with a sufficient etching resistance relative to the lower resist layer, the lithography characteristic, typically the resolution, of the upper resist layer would be frequently deteriorated, resulting in an increase of dimensional error of pattern.
As explained above, the conventional method of forming a three-layer resist pattern is accompanied with the problems that the dimension of the upper resist pattern may be caused to fluctuate due to the effect of SOG film underlying beneath the upper resist pattern, and that the re-work of lithography process in this three-layer structure becomes very troublesome.
The conventional method of forming a two-layer resist pattern, on the other hand, is accompanied with the problems that when it is desired to provide the upper resist layer with a sufficient etching resistance relative to the lower resist layer, the lithography characteristic of the upper resist layer is caused to deteriorate, resulting in an increase of dimensional error of pattern.
According to the present invention, there is provided a method of forming a pattern, which comprises:
forming a first resist film on a surface of a substrate;
patterning the first resist film to form a first resist pattern; and
forming a covering layer containing silicon or a metal on the first resist pattern by making use of a coating method using a solution containing a solvent which is incapable of dissolving the first resist.
Further, according to the present invention, there is also provided a method of forming a pattern, which comprises:
forming a first resist film on a surface of a substrate;
patterning the first resist film to form a first resist pattern;
forming a covering layer containing silicon or a metal on a surface of the first resist pattern by making use of a coating method using a solution containing a solvent which is incapable of dissolving the first resist; and
wet-etching a surface of the covering layer until a surface of the first resist pattern is exposed, thereby allowing the covering film to be selectively left remain in an opened portion of the first resist pattern;
wherein the forming of the covering layer and the step of wet-etching are continuously performed by making use of an apparatus provided with a coater and a wet etcher.
Still further, according to the present invention, there is also provided a method of manufacturing a semiconductor device, which comprises:
forming a first resist film on a surface of a substrate;
patterning the first resist film to form a first resist pattern; and
forming a covering layer containing silicon or a metal on the first resist pattern by making use of a coating method using a solution containing a solvent which is incapable of dissolving the first resist.